1. Field of the Invention
The present invention relates in general to feedback systems for adjusting the power supply input to an integrated circuit (IC) so as to stabilize signal delay through the IC and in particular to a system employing a delay circuit incorporated in the IC to sense IC signal delay.
2. Description of Related Art
The logic a programmable logic device (PLD) or a field programmable gate array (FPGA) carries out on its input signals to produce its output signal depends on how various logic blocks within the PLD or FPGA are interconnected to one another and to its input and output (I/O) terminals. We program a PLD or an FPGA by configuring its logic block interconnections. PLDs and FPGAs are frequently used instead of application specific integrated circuits (ASICs) to implement logic because an ASIC has to be specifically designed to carry out particular logic whereas a PLD or FPGA is an "off-the-shelf" component that can be easily programmed to carry out particular logic.
In many applications it is important for a logic circuit to provide a constant delay between an input signal and output signal. The delay of a signal path through an IC, whether it be an application specific integrated circuit (ASIC), a programmable logic device (PLD) or a field programmable gate array (FPGA) depends on the signal propagation delays through the transistors implementing logic gates forming the signal path. While physical characteristics of a transistor are a primary influence on its propagation delay, temperature also influences propagation delay, particularly in complementary metal oxide silicon (CMOS) transistors. A transistor's power supply voltage also influences its propagation delay. Therefore if we want an IC (particularly a CMOS IC) to provide a constant signal delay, we have to prevent variation in delay arising from changes in such factors as temperature and power supply voltage.
One approach to preventing changes in signal path delay of an IC arising from changes in power supply voltage or temperature is to keep the IC's power supply voltage and temperature at constant levels. It is a well-known technique to provide an IC with a well-regulated, substantially invariant power supply voltage. Controlling IC temperature is more problematic. Some delay stabilization systems sense the temperature of an IC and then increase or decrease the IC's temperature by turning on or off a heater as necessary to hold the sensed IC temperature within a desired range. There are many ways to sense the temperature of an IC, for example by using a temperature sensor attached to the IC or by sensing the temperature-dependent output of some electronic device implemented within the IC itself. Some systems employ an external heater attached to the IC, but external heaters waste much of the energy they produce and are difficult and expensive to thermally link to an IC. Other temperature stabilization systems include an internal heater formed by transistors implemented within the IC itself. Large heating transistors can generate substantial heat, but they can require a relatively large amount of space within the IC and can create a considerable amount of switching noise. Also since heat requires a certain amount of transit time, the loop delay in such a temperature stabilization system can make it difficult to accurately control temperature.
U.S. Pat. No. 4,789,976 issued Dec. 6, 1998 to Fujishima describes an integrated circuit implementing several delay circuits, each delaying an IC input signal to produce an IC output signal. Instead of trying to hold the temperature and power supply voltage of the IC constant, Fujishima's system adjusts the power supply voltage of the IC to compensate for any changes in delay through the delay circuits arising from changes in temperature. One of the delay circuits delays a stable reference clock signal generated by an external oscillator to produce an output indicating signal phase shifted from the reference clock signal by the amount of the delay provided by the reference delay circuit. A delay lock loop controller monitors the phase of the indicating signal in relation to the reference clock signal and adjusts the IC's power supply voltage so as to hold that phase relationship constant by holding the delay of the reference circuit constant. Since all delay circuits are of similar construction, are similar temperature, and receive the same power supply voltage, the loop controller holds the delay of all delay circuits constant.
Fujishima also describes another stabilization system in which inputs and outputs of a reference delay circuit implemented on an IC are interconnected to form a ring oscillator that oscillates with a period equal to the delay of the main delay circuit. A phase lock loop controller monitors the phase difference between the ring oscillator's output signal and an externally generated reference clock signal and adjusts the IC's supply voltage so as to phase lock the ring oscillator's output signal to the reference clock. This adjustment to the power supply voltage stabilizes the delay provided by the main delay circuit despite IC temperature changes.
While Fujishima's delay stabilization systems are effective, they require an input reference clock signal that has to have a highly stable and predictable period. In Fujishima's application such a reference clock signal is readily available as the carrier of one of the signals to be delayed. However in other applications where such a reference clock signal is not otherwise readily available, the delay stabilization system would have to include an oscillator such as a crystal oscillator which can be expensive. Also, the delay provided by Fujishima's system can't be easily adjusted to some desired level after the IC is fabricated. Thus while Fujishima's system is suitable for use in an ASIC where the desired signal delays are known at design time before the ASIC is fabricated, it may not be suitable for use in an PLD or an FPGA where desired signal delays are not known when the PLD or FPGA is fabricated.
What is needed is a delay stabilization system for an IC that does not require an external oscillator, that allows signal path delay through the IC to be accurately calibrated, and which can be easily used in connection with a conventional PLD or FPGA.